Tungsten is often used in fabricating a semiconductor integrated circuit (IC). In recent years, low-pressure chemical vapor deposition (LPCVD) techniques have been developed for depositing tungsten selectively on certain portions of an IC but not on others. See Broadbent et al, "Selective Low Pressure Chemical Vapor Deposition of Tungsten," J. Electrochem. Soc.: Solid-State Sci. & Tech., June 1984, pp. 1427-1433. Also see Saraswat et al, "Selective CVD of Tungsten for VLSI Technology," VLSI Sci. & Tech./1984, Vol. 84-7, pp. 409-419. The ability to selectively deposit tungsten has significantly increased its usefulness, particularly in IC's of the complementary metal-oxide semiconductor (CMOS) type.
FIGS. 1a-1e show an example of how tungsten is so employed in manufacturing a p-channel insulated-gate field-effect transistor (FET) of a conventional CMOS-type IC. At the stage indicated in FIG. 1a, a thick field-oxide region 10 laterally surrounds part of a major n-type region 12 of a monocrystalline silicon substrate to define an active semiconductor island along the top of the substrate. An n-doped polycrystalline silicon (polysilicon) gate electrode 14 has been formed on a thin oxide dielectric layer 16 lying along the upper surface of n region 12.
Turning to FIG. 1b, a thin oxide layer 18 is grown from the exposed silicon in conjunction with the formation of oxide spacers 20 on portions of oxide layer 18 along the sides of electrode 14. Using field oxide 10 and the composite structure formed by electrode 14 and the surrounding oxide as a mask, ions 22 of a boron-containing species are implanted through layer 18 into n region 12 to form a pair of highly doped p-type regions 24 along the upper surface of the substrate.
The structure is then annealed in an inert high-temperature environment to activate the implanted boron and repair lattice damage. The implanted boron redistributes slightly during the anneal. As a result, p+ regions 24 expand downward and sideways as generally indicated in FIG. 1c to become the source/drain elements of the FET.
An electrical interconnection system for the various IC components is now formed. The portions of layer 18 along the tops of region 12 and electrode 14 are removed (except for the oxide under spacers 20) to expose the underlying silicon. See FIG. 1d. A selective tungsten deposition is performed by reducing tungsten hexafluoride under LPCVD conditions such that tungsten accumulates on the exposed silicon but not on the adjacent oxide. The result is the structure of FIG. 1e in which tungsten layers 26 and 28 respectively lie on elements 14 and 24. This structure is, for example, described in Metz et al, "Effect of Selective Tungsten as a Polysilicon Shunt on CMOS Ring-Oscillator Performance," IEEE Electron Device Lett., July 1985, pp. 372-374. The interconnection system is finished by forming a patterned electrically conductive layer (not shown) that suitably contacts W layers 26 and 28.
The same steps are employed in forming an n-channel insulated gate FET in the CMOS-type IC, with two notable differences. Firstly, the monocrystalline silicon conductivities are reversed. Secondly, the source/drain elements of the n-channel FET are normally created by a double n-type ion implant typically consisting of a low dose of phosphorus and a high dose of arsenic. The phosphorus implant is performed before creating oxide spacers along the sides of the gate electrode. The boron implant to form p+ regions 24 of the p-channel FET follows both the arsenic implant and an anneal performed in a high-temperature oxidizing environment to activate the implanted arsenic. Part of the thickness of oxide layer 18 is produced by the silicon oxidized during this anneal.
One problem with selective deposition of tungsten onto monocrystalline silicon by LPCVD reduction of WF.sub.6 is that "tunnels" are produced in the annealed silicon near the tungsten/silicon interface. The formation of these tunnels is described in: DeBlasi et al, "Interfacial Tunnel Structures in CMOS Source/Drain Regions Following Selective Deposition of Tungsten," presented at Mat. Res. Soc. Symp., Apr. 1986, published in Mat. Res. Soc. Symp. Proc., Vol. 71, 1986, pp. 303-307; Stacy et al, "Interfacial Structure of Tungsten Layers Formed by Selective Low Pressure Chemical Vapor Deposition," J. Electrochem. Soc.: Solid-State Sci. & Tech., Feb. 1985, pp. 444-448; and Paine et al, "Microstructural Characterization of LPCVD Tungsten Interfaces," presented at Mat. Res. Soc. Workshop, Oct. 1985, published in Tungsten and Other Refractory Metals for VLSI, 1986, pp. 117-123. Tunnels are a concern because they may detrimentally affect IC performance and/or reliability.
The location and number of tunnels seems to depend on the dose of the implanted species. With a low dose of arsenic or boron (or with no implantation at all), a large number of tunnels are produced in the annealed silicon near the periphery (or perimeter) of the W/Si interface. If the arsenic dose is high, few (if any) tunnels are produced. Conversely, a high boron dose leads to a very large number of tunnels. Furthermore, the tunnels are located along the entire extent of the W/Si interface, not just at the periphery.
High doses of arsenic and boron are normally employed in fabricating the source/drain elements of the CMOS-type IC described above. The problem of tunnel formation is thus particularly acute in the boron case.
The mechanism that causes tunnels is not well understood. Implantation of boron produces extended defects--i.e., dislocation loops and stacking faults--in the silicon near where the ions enter. However, the subsequent anneal eliminates virtually all the extended defects near the implantation surface. It appears that something besides extended defects must be responsible for the tunnels described in the preceding references. In any case, it is quite desirable to have a technique that lessens tunnel formation in boron-implanted silicon on which tungsten is selectively deposited.